This document will serve to introduce the reader to use of the AMS design Kit within Synopsys, and allow show the user how to guide a design from VHDL code through Synopsys through to place and route in the Cadence toolset. A basic knowledge of synopsys is assumed throughout this document, if not refer to the introductory guide located at www.ee.qub.ac.uk/dsp/support/documentation/synopsys_intro.html, before proceeding any further.

1. Setting up your Unix environment to use the Design Kit

For a design to be implemented in a logical fashion we will first create a directory for the synthesis stage of the process and a directory for the layout and post processing stage of the design process. This means that the hierarchy will resemble that shown in figure 1.1

 

Figure 1.1 Directory Hierarchy



 

You may create the directory structure using the mkdir command as follows:

 

mkdir design_directory

mkdir design_directory/layout

mkdir design_directory/ synthesis

mkdir design_directory/synthesis/WORK

mkdir design_directory/synthesis/src

 

Now copy the source files for this exercise from the tutorial directory with the command:

 

cp /home/user2/oz/tutorials/ams_design_route/synthesis/src/*.vhd design_directory/synthesis/src

 

We must now ensure that variables required for the design kit are added to users .cshrc file. Using the text editor of your choice ensure that the following lines asre added to the user.cshrc file located in your home directory (where user is your unique Unix username).

 

setenv AMS_DIR /apps/design_kits/ams/cadence97/

setenv CDSDIR /apps/cadence_97

set path = ($path $AMS_DIR/artist/bin)

alias ams_synopsys /apps/design_kits/ams/cadence97/programs/bin/ams_synopsys

 

Once these have been added to the file you can, either exit the system and log back on or alternatively source the file with the command:

 

source ~/user.cshrc

 

We must now copy files from the design kit into our synthesis directory to setup initial variables for synopsys. Issue the following command at the prompt:

 

cp $AMS_DIR/synopsys/cub/.synopsys design_directory/synthesis/.synopsys_dc.setup

 

Again you will need to know the target technology required, the cub in the command shown is a 0.6u three layer metal digital library. You will also need to create a .synopsys_vss.setup file for library management in synopsys in the synthesis directory with the initial values as shown. Again use a text editor of your choice for this.

 

TIMEBASE = NS

TIME_RES_FACTOR = 0.1

WORK > DEFAULT

DEFAULT : ./WORK

 

You can now proceed to the next stage, which is to load up the design in synopsys and synthesize For this example now copy the example files from the tutorial subdirectory with the command:.

 

cp /home/user2/oz/tutorials/synopsys/src/*.vhd design_directory/synthesis/src

 

 

1.1 Starting the Synopsys Toolset

Start the synopsys toolset with the command:

 

ams_synopsys –g

 

This opens up a window as shown in Figure 1, the main Design Analyzer window.

 

Figure 1



Now we will first read in our files by using the menu command:

File -> Read

 

This opens up a new window as shown in Figure 1.2, the file read dialog box.

 

Figure 1.2

Use the mouse to locate the source code for the package in the src subdirectory, and click on the tablet_package_synth.vhd. A new window opens up showing a transcript of the vhdl compilation process. This should compile with no errors (but with several warnings due to the way the code was written). Now repeat this process for the top level circuit description tablet_project_synth.vhd, again there should be no compilation errors.

 

Once the file has been compiled you will see a series of blocks displayed in the design analyzer window. Locate the item called tablet_project_synth and double click on it. The window now changes so that we see a symbol for the top level circuit with input and output pins. We will now start the synthesis and mapping process.

 

2. Design Synthesis

Since the design contains multiple instances of the same circuit element we must first uniquify the design hierarchy (since the design contains multiple instances of circuits whose beahviour is described in the package we must give each individual occurrence a unique name). To do this select from the menu bar:

 

Edit -> Uniquify -> Hierarchy

 

Once the design is uniquified we can now proceed to add attributes to the design. Select the tablet_in port, this is effectively a clock input. In order for the design to be optimized correctly we must add constraints. Select from the menu bar (with the clock pin highlighted):

 

Attributes -> Clocks -> Specify

 

This opens up a new window as shown in Figure 1.3

 

Figure 1.3

We can leave the values at the initial default values as this design is not a speed critical application. For other designs you may need to specify a higher clock frequency (this is running at 20 MHz).Click on the Apply button, and then click on the Cancel button to dismiss the window.

 

We will now add input and output pads to the design by selecting first the input pads and then from the menu bar:

 

Attributes -> Optimization Directives -> Input Port

 

This opens up a window as shown in Figure 1.4

Figure 1.4

Now click on the port is pad button and then click on the Apply button and then the Cancel to dismiss the window. Repeat this procedure for the output pins by selecting the output pins and then selecting from the menu bar:

 

Attributes -> Optimization Directives -> Output Port

 

Now set the operating parameters for the circuit by selecting from the menu:

 

Attributes -> Operating Environment -> Operating Conditions

 

This opens up a window as shown in Figure 1.5

Figure 1.5

Use the scroll bar and highlight the typical option and select the OK button. Now you can set up more attributes for the design i.e. wire load models and whether or not the design is speed or area critical. These decisions will be left to the user.

 

We will now go and synthesis the design by selecting from the menu bar:

 

Tools -> Design Optimization

 

This opens a window as shown in Figure 1.6

Figure 1.6

Select the OK button and the circuit is synthesized to a generic rtl description and then the description is mapped to available cells in the particular technology. For larger designs this may take a while. You should be able to watch the process in the Compile log window. Once complete we must now save the synthesized design in a format suitable for import into our back end toolset (in this case Cadence). We must now setup some of the parameters required for saving in verilog format. Select from the menu bar:

 

Setup -> Command Window

 

In the window that now opens up enter the following commands:

 

change_names -rules verilog -hierarchy -verbose > change_names

 

Now to save the design, select from the menu bar:

 

File -> Save As

 

This opens a window as shown in Figure 1.7 the Save As Dialog Box.

Figure 1.7

Enable the Save All Designs button and ensure that the format is set to verilog and the filename is set to tablet_project_synth.v and click on the OK button. The design is now saved in verilog in the current directory. You can now exit the Design Analyzer program and proceed to the next stage, which is to import the verilog netlist created earlier into Cadence for place and route.

 

 

2. Importing the Design into Cadence

When you have returned back to the operating system, you will need to copy the verilog netlist from the synthesis directory into the layout directory before running Cadence tools. The reason for this is to keep the design hierarchy in a sensible order, if for some reason we need to scrub the layout directory then at least we still have the original synthesized netlist in a separate subdirectory. Change directory to the layout directory and issue the following command:

 

cp ../synthesis/tablet_project_synth.v .

 

Once you have copied the file then start the Cadence Toolset by typing at the command prompt:

 

ams_cds –tool artist –tech csd –mode fb

 

This opens a window as shown in Figure 2.1 The Main Cadence Window. The command tells the cadence software to use the cub technology and the mode is fb or front to back, unsing the analog artist suite of tools. The AMS design kit in general is a mixed mode i.e. both analog and digital technology but the csd library is purely a 0.6u 3 layer metal digital library which is why we are using the analog artist toolset.

Figure 2.1



In addition to this window a library manager window is opened up on your display as well. Minimize the library manager window and we will now proceed to import the verilog netlist. But first we must create a new library into which we import the design, to do this select from the main Cadence menu bar:

 

File -> New -> Library

 

This opens a window as shown in Figure 2.2

Figure 2.2

Enter DESIGNS as a suitable library name, and enable the Attach to Techfile button. Now select the OK button, after a few moments a new window appears as shown in Figure2.3

 

Figure 2.3

Ensure that the technology is set to TECH_CUQ and select the OK button. A new library is now created with all required technology files. You will now import the verilog netlist created earlier with synopsys into the DESIGNS database by selecting from the menu bar:

 

File -> Import -> Verilog

 

This opens a window as shown in Figure 2.4 the Import Verilog Dialog Box

Figure 2.4



Now ensure that the following entries are made in the dialog box:

 

Target Library Name DESIGNS

Reference Libraries sample basic HRDLIB

Input File(s) tablet_project_synth.v

-f options /apps/design_kits/ams/cadence97/artist/AMS_TH06_1/veritools/VERILOGIN.inc

 

We also have the option of importing the design as a netlist or a schematic. Since the majority of designs undertaken by the DSPgroup will be large we will import the design as a netlist rather than tell Cadence to try and construct a schematic for the design. Also ensure that the Overwrite existing views button is enabled, then select OK. After a few moments you will see a new window which will prompt you to look at the log file of the Verilog import process. Inspect this file and you should see warnings but no errors.

 

To proceed we must now open up the netlist in a Composer window. To do this select from the menu bar:

 

File -> Open

 

In the Library Manager window that now appears as shown in Figure 2.5 select the DESIGNS library and then, tablet_project_synth as the Cell name and netlist as the view. Then from the Library Manager window select

 

File -> Open

 

Figure 2.5

After a few moments the Composer window now opens, the window shows symbols for all the circuit elements superimposed upon one another. We now wish to initialize the floorplanning software so select from the Composer window menu bar:

 

Tools -> FloorPlan/Netlist

 

The tool bar on the Composer is now updated and select :

 

FloorPlan -> Hierarchy Browser

 

In the pop up dialog box that now opens ensure that netlist is in the View name field, and select the OK button. A window as shown in Figure 2.6 opens, this is the Hierarchy Browser window

 

Figure 2.6



Click on the tablet_project_synth box and select from the menu bar:

 

Hierarchy -> Expand Selected

 

You should now see the hierarchy of the design in the window. To generate the required information to start layout select from the menu bar:

 

Hierarchy -> Generate Physical Hierarchy

 

Look in the main Cadence window for a transcript of the program’s execution, if there are any errors go back and correct the error. You can now close down both the Composer and Hierarchy Browser windows by selecting from their respective menu bars:

 

Window -> Close

 

3. Performing Place and Route on the Design

 

Once the design has been successfully imported into the Cadence database we will now need to place and route the design. Since the design is quite small we will do the place and route as a flat structure. For hierarchical place and route refer to the document located at http://www.ee.qub.ac.uk/dsp/support/documentation/cadence/hierarchy which contains more information about floorplanning and soft block/macro creation. To open the AutoLayout view created in the earlier session with Hierarchy Browser select from the main Cadence menu bar:

 

File -> Open

 

The Library Manager window now opens up, in this window select the following items:

 

Library DESIGNS

Cell: tablet_project_synth

View: AutoLayout

 

A new window opens up as shown in Figure 3.1, this is theVirtuoso window.

Figure 3.1

In this window you see all the cells laid out not to enable place and route select from the menu bar:

 

Tools -> FloorPlan/P&R -> Cell Ensemble

 

This activates more options in the toolbar and note the title of the window now changes from Virtuoso to Cell Ensemble. In addition a new window opens up which cannot be closed down until the Cadence toolset is closed this is the Object Selection Window or OSW. You can minimize this for the meantime by clicking on the minimize widget. Now initialize the floorplan by selecting:

 

FloorPlan -> ReInitialize

 

This now creats a default region into which all the cells can be placed and places the cells outside the region for subsequent place and route. The Cell Ensemble Window noew resembles that shown in Figure 3.2

 

Figure 3.2 FloorPlan after ReInitialization

To place the cells once the core has been initialized select from the menu bar:

 

Place -> Automatic

 

This opens a dialog box as shown in Figure 3.3

 

Figure 3.3

Ensure that the following options are entered in the various fields:

 

Insert FeedThru: On

FeedThru Library Name: HRDLIB

FeedThru Master Name: FEED

FeedThru Master View: abstract

Placement Snap Grid: 0.1

 

Then select the OK button. The cells in the design are now placed in rows, and the software tries to ensure that the design takes up as little silicon area as possible by adjusting the aspect ratio to ensure 1:1. It is possible at the start of this process to adjust the apsect ratio of the design if required, again this will be discussed in more detail in an advanced topics section.

 

Once the design has been placed you can now save it as with a new CellView in this instance placed. To do this select from the Cell Ensemble menu:

 

Design -> Save As

 

This opens a new dialog box into which enter the following information:

 

Library Name: DESIGNS

Cell Name: tablet_project_synth

View Name: placed

Then click on the OK button and the design is saved with the new view name. We now wish to route the design, to start the process we must first initialize channels in which routing will take place. To do this select from the menu bar:

 

Route -> Channels -> Create

 

This opens a dialog box as shown in Figure 3.4.

 

Figure 3.4

Accept the defaults and click on the OK button.

 

Now to initially route the design select from the menu bar:

 

Route -> Global Route -> Automatic

 

Accept the default options in the dialog box that opens, by selecting the OK button. You can watch the programs progress in the main Cadence window and check for errors/warnings. When this is complete select from the menu bar:

 

Route -> Detail Route -> Automatic

 

The detail of the routing is now carried out. Again look in the CIW to check for any errors, you may also see messages about how routing channels have been shrunk or expanded. Now to view the whole design with routing select from the menu:

 

Design -> Options -> Display

 

In the box that opens up leave all options to their defaults except the Display level. Change this to be 0 to 5 layers visible and select the OK button. This dismisses the window and the design appears as shown in Figure 3.5

 

Figure 3.5



Congratulations you have now completed this part of the exersize. Now save the design with an appropriate view name such as p&r.

 

 

4. Extracting Layout Information

 

We wish to use information from the layout and feed it back into our synopsys model. The mechanism by which we do this is with sdf (standard delay files) and spf (standard parasitic files) files. The main aim of this section is to show the reader how to extract information from layout to be used for subsequent post layout simulation of the design. The first stage of this process is to extract parasitic information from the design, to do this select:

 

Analyze -> Parasitics -> Extract

 

In the dialog box that opens up select the OK button. A point to remember at this stage is that for larger designs this process can be time consuming, so only do this when you actually need to. After the parasitics are extracted you can then produce an spf file by selecting:

 

Analyze -> Parasitics -> Write Reduced SPF

 

In the dialog box that opens ensure that the name is set to something sensible like tablet_project_synth.spf and that name mapping is set to logical. Now select the OK button. If you drop back to a Unix shell you will now find a file called tablet_project_synth.spf in your design directory.

 

We now wish to create the sdf file, to do this select from the menu:

 

Analyze -> Delays -> Compute

 

Again accept the default values on select the OK button. You will be prompted once again to verify this action as this can take some time to complete for larger designs. Once this is complete you can now create the sdf file by selecting:

 

Analyze -> Delays -> Write SDF

 

Again choose a sensible name for the sdf file i.e. tablet_project_synth.sdf and select the OK button. Once complete you can now close down any Cadence windows that remain open.

 

5. Further Topics

Comments to a.cassidy@ee.qub.ac.uk