Introduction

Research Activities

Nanotechnology

System On Chip

Microelectromechanical Systems (MEMS)

Integrated Circuits and Electronic Devices

Silicon On Insulator (SOI)

Metallisation

Materials and Technology

Microelectronic Device Simulations

Research Opportunities

Research Contacts

Laboratory & Facilities

NISRC Members Only

CCD Technology

(by Dr. Fred Ruddell and Dr. John Montgomery)

A 10-mask process has been designed and implemented to fabricate buried n-channel back-illuminated 3-phase CCDs.  The mask design incorporates 8x8 and 16x16 arrays based on a 30x30µm pixel size, and employing a single readout register with charge sensing performed by a floating diffusion structure linked to a single source follower transistor.  A wide range of test structures has been included in the design to permit measurement of layer resistivities, gate dielectric quality, field threshold voltage, gate length effects, etc.  Mask set production has been carried out in the QUB NISRC facility.

Mask Layout for CCDs Fabrication