Introduction

Research Activities

Nanotechnology

System On Chip

Microelectromechanical Systems (MEMS)

Integrated Circuits and Electronic Devices

Silicon On Insulator (SOI)

Metallisation

Materials and Technology

Microelectronic Device Simulations

Research Opportunities

Research Contacts

Laboratory & Facilities

NISRC Members Only

Self Heating in SOI

(by Prof. Alastair Armstrong)

SOI devices  exhibit self heating effects. These arise  because the device is thermally insulated from the substrate by the buried oxide layer. This leads to a substantial elevation of temperature within the SOI device, which consequently modifies the output IV characteristics of the device. These effects must be taken into account by device technology engineers and designers. TCAD models heat generation, heat flow, lattice heating, heat sinks and effects of local temperature on physical constants. Thermal and electrical effects are coupled through self-consistent calculations In Figure 1  the temperature distribution within an SOI transistor is shown.

Figure 1.  Self heating in SOI transistors has an important  effect on drain current.

SOI devices also exhibit several parasitic phenomena which are related to impact ionization in the high electric field that occurs near the drain and the fact that the body of the device is floating. TCAD allows pictorial representation of the electric field  and other physical variables inside the device structure.

Negative resistance arises due to the reduction in mobility due to temperature rise in the SOI layer at high power dissipation i.e. high gate voltage.

Figure 2.  Effect of self heating on output characteristics.

A series of one dimensional  ‘cut lines’ in the vertical direction enables visualation of the variation of electron density changes with SOI layer thickness from 1.5 nm to 20 nm at a specified gate voltage.

References

1. Armstrong, G.A. Brotherton S.D. and Ayres, J.R. "A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors",  Solid State Electronics, 39, 1996, pp.1337-1346.

2. Armstrong, G.A., Brotherton S.D. and Ayres, J.R., "Simulation of transient emission in polysilicon thin film transistors", Solid State Electronics, 40, 1997, pp 835-844.             

3. Armstrong G.A. and Gamble H.S. "Simulation of self heating effects in heterojunction bipolar transistors fabricated in wafer bonded SOI substrates" in Silicon-on-Insulator technology and devices IX, P. Hemment Editor , Electrochemical Society, 1999, p.249-254.

4. Baine P.T., Uppal S., Armstrong G.A., Mitchell SJN and Gamble H.S. " Thermal vias for SOI technology", Proc ICCCD International Conference on Communications, Computers and Devices, Kharagpur, India, 2000, p.239-242.