Introduction

Research Activities

Nanotechnology

System On Chip

Microelectromechanical Systems (MEMS)

Integrated Circuits and Electronic Devices

Silicon On Insulator (SOI)

Metallisation

Materials and Technology

Microelectronic Device Simulations

Research Opportunities

Research Contacts

Laboratory & Facilities

NISRC Members Only

SOI Simulation

(by Prof. Alastair Armstrong)

TCAD can be used to visualise the device structure. In Figure 1 we see from the 2D doping profile  how the active layer of the SOI transistor has been  isolated by local oxidation.

Figure 1.  Short channel SOI MOSFET created using ATHENA.

Device simulator ATLAS determines terminal currents as a function of gate voltage. Graphical visualisation software allows current to be plotted on either a linear or a logarithmic scale.

Figure 2.  Simulated Id vs. Vg characteristics for a short channel MOSFET.

A series of one dimensional  ‘cut lines’ in the vertical direction enables visualation of the variation of electron density changes with SOI layer thickness from 1.5 nm to 20 nm at a specified gate voltage.

Figure 3.  Influence of silicon film thickness on distribution of electrons in a double gate MOSFET.

References

1. Armstrong, G.A. and French, W.D. "Suppression of parasitic bipolar effects in thin film SOI transistors", IEEE Trans Elect Dev. Lett. EDL-13, 1992, pp.198-200.

2. Armstrong, G.A. and French, W.D. "Simulation of ultra thin film SOI transistors using a non-local model for impact ionisation", Solid State Electronics, 35, 1992, pp.1761-1770.

3. Alam M.S. and Armstrong G.A. “Extrinsic Parameter Extraction for RF CMOS” Solid State Electronics, 48, 2004, pp.669-674.

4. Jankovic N. and  Armstrong G.A., “Performance comparison of double gate SOI MOSFETs on highly doped and near intrinsic layers”, Microelectronics Journal, 35, 2004, pp.647-654.